V850E/IA2

主要特色：

Operating voltage: 4.5 to 5.5 V
Max. frequency: 40 MHz
ROM capacities: V850E/IA3 128 KB mask ROM and 128 KB flash memory/ V850E/IA4 128 to 256 KB mask ROM and 128 KB flash memory
RAM capacities: V850E/IA3 6 KB/ V850E/IA4 6 to 12 KB
Package: 100-pin plastic LQFP package
Number of instructions: 80
Minimum instruction execution time: 25 ns (@ internal 40 MHz operation)
General-purpose registers: 32 bits x 32 registers
Instruction set (V850E1 CPU):

• Signed multiplication (32 bits x 32 bits -> 64 bits): 1 or 2 clocks
• Saturated operation instructions (with overflow/underflow detection function)
• 32-bit shift instruction: 1 clock
• Bit manipulation instructions
• Long/short format load/store instructions
• Signed load instructions

Memory space:

• 4 MB linear address space (shared by program and data)
• Chip select output function: 8 spaces
• Memory block division function: 2, 4, or 8 MB/block
• Programmable wait function
• Idle state insertion function

External bus interface:

• 16-bit data bus (address/data multiplex)
• 16-/8-bit bus sizing function
• External wait function

Interrupts/exceptions:

• External interrupts: 16 (including NMI)
• Internal interrupts: 42 sources
• Exceptions: 1 sourse
• 8 levels of priority definable

DMA controller: 4-channel configuration

• Transfer unit: 8 bits/16 bits
• Maximum transfer count: 65,536
• Transfer type: 2-cycle transfer
• Transfer modes: Single transfer, single-step transfer, block transfer
• Transfer subjects: Memory <-> Memory, Memory <-> I/O, I/O <-> I/O
• Transfer requests: On-chip peripheral I/O, software
• Next address setting function

I/O ports: Input ports 6 , I/O ports 47
Timer/counter function:

• 16-bit timer for 3-phase sine wave PWM inverter control: 2 channels
• 16-bit up/down counter/timer for 2-phase encoder input: 1 channels
• General-purpose 16-bit timer/counter: 2 channels
• General-purpose 16-bit timer/event counter: 1 channel
• 16-bit interval timer: 1 channel

Serial interface:

• Asynchronous serial interface (UART): 2 channels
• Clocked serial interface (CSI): 2 channels

NBD (Non Break Debug) function: 1 channel (µPD70F3116 only)

• RAM monitoring
• Event detection

10-bit resolution A/D converter: 6 channels + 8 channels(2 units)
Regulator:
Two power supplies, one for the internal CPU and one for the peripheral interface, are not necessary.
A 5 V single-power-supply system can be configured by connecting an N-ch transistor (2SD1950 (VL standard product, surface mount type) or 2SD1581 (independent type) is recommended).
If a 3.3 V power supply is available, it can be directly connected to the REGIN pin.
Clock generator:

• Multiplication function (x1, x2.5, x5, x10) using PLL clock synthesizer
• Divide-by-2 function using external clock input

Power-saving function: HALT, IDLE, and software STOP modes
CMOS technology: Full static circuits