The SH7616 is a CMOS single-chip microcontroller that integrates a
high-speed CPU core using an original Renesas architecture with supporting
functions required for an Ethernet system.
The CPU has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically operates at a rate of one instruction per cycle, offering a great improvement in instruction execution speed. In addition, the 32-bit internal architecture provides improved data processing power, and DSP functions have also been enhanced with the implementation of extended Harvard architecture DSP data bus functions. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as realtime control, which could not previously be handled by microcontrollers because of their high-speed processing requirements. The SH7616 also includes a maximum 4-kbyte cache, for greater CPU processing power when accessing external memory.
The SH7616 is equipped with a media access controller (MAC) conforming to the IEEE802.3u standard, and an Ethernet controller that includes a media independent interface (MII) standard unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system configuration are also provided, including RAM, timers, a serial communication interface with FIFO (SCIF), interrupt controller (INTC), and I/O ports.
To improve the efficiency of frame transmission/reception, the processing power of the DMAC for the Ethernet controller is improved and the FIFO for the DMAC has 2 kbytes. A CAM match signal input function is provided for systems that require multiple MAC addresses. In serial I/O with three channels, one operates with the FIFO for better data processing power when connected to the codec.
- High-performance RISC engine, SH2-DSP core with enhanced DSP functions
- 80 MIPS and 125 MOPS achieved at 62.5 MHz
- Cache for both instructions and data (4 kbytes)
- 4-way set-associative cache with 64 entries and a line length of 16 bytes
- On-chip RAM (8 kbytes)
- SDRAM interface
High-speed accessibility (external bus clock: 62.5MHz max.)
16-byte DMA dual burst access (for memory-to-memory copying)
- Dedicated DMAC for Ethernet Controller (E-DMAC)
Two independent channel DMAC for each Tx and Rx
Transfer possible between EtherC and external memory / on-chip memory
16-byte burst transfer possible
- Ethernet controller (MAC*: conforms to IEEE802.3u)
Transfer rate: 10 or 100 Mbps, full-duplex transfer supported
Data frame assembly and disassembly, and CRC processing supported Conforms to MII** and Magic Packet TM*** standards
Built in FIFO (512B each for Tx and Rx : SH7615) (2kB each for Tx and Rx : SH7616)
CAM (Contents Addressable Memory) Interface :7616
- Serial debugging function (JTAG)
- Peripheral functions
Includes SCIF, DMAC, INTC, TPU, WDT, FRT, SIO and I/O ports
- Power management functions
Separate clock signals can be assigned for the CPU core, peripheral modules, and external bus.
Sleep, standby, and module standby modes provided
- Vcc = 3.3 V (5-V interface supported for I/O and Ethernet pins)
*: MAC: Media Access Controller
**: MII: Media Independence Interface
***: Magic Packet is a trademark of AMD, Inc., USA.
Network applications, OA equipment, surveillance cameras, etc.